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MCHStreamer data alignment in I2S mode 1 month 2 weeks ago #65165

  • Vasiliev
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Hello!
I'm using MCHStreamer in I2S mode connecting it to ADI's codec evaluation board.
ADI's I2S is configured to 24-bit (I2S mode), and ASIO audio driver provides 32-bit integers with no other options.
The question is how the recorded data are aligned by audio driver in such use-case?

The problem is that my recordings level is very low and I suggest that audio driver can put 24-bits received by I2S to the lower part of int32 instead of aligning data by MSB.
The issue can be related either to the recording software (using Adobe Audition) or to the audio driver.

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MCHStreamer data alignment in I2S mode 1 month 1 week ago #65239

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Maybe double check with a scope that the timing diagram is the same as per our manual? 
If the board is correctly config to 64FS I2S Slave, it doesn't matter if the MCHStreamer is outputting 24/32bits. The receiver board will automatically ignore the lower 8bits. 

Most likely something is going on here in you ADI board.. remember that we're always Master. 

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MCHStreamer data alignment in I2S mode 1 month 1 week ago #65241

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Thanks for share !!! 

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MCHStreamer data alignment in I2S mode 1 month 1 week ago #65243

  • Vasiliev
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Maybe double check with a scope that the timing diagram is the same as per our manual? 
If the board is correctly config to 64FS I2S Slave, it doesn't matter if the MCHStreamer is outputting 24/32bits. The receiver board will automatically ignore the lower 8bits. 

Most likely something is going on here in you ADI board.. remember that we're always Master. 

Devteam

The ADI board's serial ports are configured to 24-bit Slave using I2S mode data transfer. As far as I understand the mode description, data are sent one bit-clock after frame clock edge.
Thus, the question can be split for two:
1) what is the data delay expected by MiniDSP: no delay (left justified), 1 clock (typical I2S), any other value?
2) how the data are aligned in 32-bits samples provided by audio driver if a device provides less than 32-bits: with significant bits start from MSB or aligned to LSB?
I suggest that you have answered to the second question that data are stored starting from the MSB while they are received (with lower bits set to 0 by I2S protocol).
Is that correct?
As for the first question, there is a figure in the user's manual, from which I can suppose that the expected I2S data sending mode includes 1-clock delay after frame edge.
Again, I need some confirmation for that.

If both suggestions (1-bit latency + MSB alignment) are correct, than the problem with signal level is explained either with recording software or my microphone's sensitivity (-43 dB). I'll look for some calibrated sound generator for verifying that.

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